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DM74ALS652 Octal 3-STATE Bus Transceiver and Register
October 1986 Revised March 2000
DM74ALS652 Octal 3-STATE Bus Transceiver and Register
General Description
This device incorporates an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus or internal register to bus. This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high level logic drive provide this device with the capability of being connected directly to and driving the bus lines in a bus organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The registers in the DM74ALS652 are edge-triggered Dtype flip-flops. On the positive transition of the clock (CAB or CBA), the input data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data and a HIGH level selects stored data. The select controls have a "make before break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data. The enable (GAB and GBA) control pins provide four modes of operation: real-time data transfer from bus A to B, real-time data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal stored data transfer to bus A and/or B.
Features
s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s 3-STATE buffer-type outputs drive bus lines directly s Independent registers and enables for A and B buses s Multiplexed real-time and stored data
Ordering Code:
Order Number DM74ALS652WM DM74ALS652NT Package Number Package Description M24B N24C 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
(c) 2000 Fairchild Semiconductor Corporation
DS009174
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DM74ALS652
Function Table
Inputs GAB X L L L L L H H H L H GBA H X H H L L H H H L L CAB H/L H/L X X X H or L CBA H/L H/L X H/L X H or L SAB X X X X X X L X X (Note 2) X H SBA X X X X L H X X X X (Note 2) H Data I/O (Note 1) Operation or Function A1 thru A8 Input Not Specified Input Input Output Output Input Input Input Output Output B1 thru B8 Not Specified Store A, Hold B Input Input Input Input Input Output Output Output Input Output Store B, Hold A Store A and B Data Isolation, Hold Storage Real-Time B Data to A Bus Stored B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Store A in both Registers Store B in both Registers Stored A Data to B Bus and Stored B Data to A Bus
H = HIGH Logic Level L = LOW Logic Level X = Don't Care (Either LOW or HIGH Logic Levels, including transitions) H/L = Either LOW or HIGH Logic Level excluding transitions = Positive-going edge of pulse Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Note 2: Select control = L; clocks can occur simultaneously Select control = H; clocks must be staggered in order to load both registers.
Logic Diagram
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DM74ALS652
Absolute Maximum Ratings(Note 3)
Supply Voltage Input Voltage Control Inputs I/O Ports Operating Free-Air Temperature Range Storage Temperature Range Typical JA N Package M Package 44.5C/W 80.5C/W 7V 5.5V 0C to +70C -65C to +150C
Note 3: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
7V
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Pulse Duration, Clocks Low or High Data Setup Time, A before CAB or B before CBA (Note 4) Data Hold Time, A after CAB or B after CBA (Note 4) Free Air Operating Temperature 0 70 C
Note 4: = with reference to the LOW-to-HIGH transition of the respective clock.
Parameter
Min 4.5 2
Nom 5
Max 5.5 0.8 -15 24
Units V V V mA mA MHz ns ns ns
0 12.5 10 0
40
Electrical Characteristics
over recommended free air temperature range Symbol VIK VOH Parameter Input Clamp Voltage HIGH Level Output Voltage VOL LOW Level Output Voltage II IIH IIL IO ICC Input Current at Maximum Input Voltage HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current VCC = Max, VI = 0.4V (Note 5) VCC = Max, VO = 2.25V VCC = Max Outputs HIGH Outputs LOW Outputs Disabled
Note 5: For I/O ports the 3-STATE output currents (IOZH and IOZL ) are included in the IIH and IIL parameters.
Test Conditions VCC = Min, II = -18 mA VCC = 4.5V to 5.5V VCC = Min VCC = Min IOH = -0.4 mA IOH = -3 mA IOH = Max IOL = 12 mA IOL = 24 mA IOL = 48 mA VCC = Max I/O Ports, VI = 5.5V Control Inputs, VI = 7V VCC = Max, VI = 2.7V, (Note 5) Control Inputs I/O Ports
Min VCC - 2 2.4 2
Typ
Max -1.2
Units V V
3.2 0.25 0.35 0.35 0.4 0.5 0.5 100 100 20 -200 -200
V
A A A mA mA
-30 47 55 55
-112 76 88 88
3
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DM74ALS652
Switching Characteristics
over recommended operating free air temperature range (Note 6) Symbol tPLH tPHL tPLH tPHL tPLH Parameter Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output (with A or B LOW) (Note 6) tPHL Propagation Delay Time HIGH-to-LOW Level Output (with A or B LOW) (Note 6) tPLH Propagation Delay Time LOW-to-HIGH Level Output (with A or B HIGH) (Note 6) tPHL Propagation Delay Time HIGH-to-LOW Level Output (with A or B HIGH) (Note 6) tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output SBA or SAB to A or B GBA to A GBA to A GBA to A GBA to A GAB to B GAB to B GAB to B GAB to B 3 17 ns 5 20 ns SBA or SAB to A or B 6 25 ns SBA or SAB to A or B 6 20 ns SBA or SAB to A or B 12 35 ns Conditions VCC = 4.5V to 5.5V, CL = 50 pF, R1 = R2 = 500, TA = Min to Max From (Input) To (Output) CBA or CAB to A or B CBA or CAB to A or B A or B to B or A A or B to B or A Min 10 5 5 3 Max 30 17 18 12 Units ns ns ns ns
5
18
ns
1
10
ns
2 6 6 1 2
16 22 18 10 16
ns ns ns ns ns
Note 6: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
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DM74ALS652
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
5
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DM74ALS652 Octal 3-STATE Bus Transceiver and Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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